1. Technical Field
Various embodiments of the present disclosure generally relate to a semiconductor integrated circuit, and more particularly, to a test circuit, a semiconductor memory apparatus using the same, and a test method of the semiconductor memory apparatus.
2. Related Art
To improve reliability of a semiconductor memory apparatus, a test is generally performed to determine whether or not leakage current occurs between a word line and a bit line. This test is referred to as an Unlimited Sensing Delay (USD) test, in which the occurrence of leakage current between the word line and the bit line serves as a criterion on how long data stored in a memory cell will be retained.
FIG. 1 is a diagram schematically showing a configuration of a typical semiconductor memory apparatus having an open bit line structure. In FIG. 1, the bit line is represented as BL.
In a typical USD test, a logic low data is inputted to all mats of the semiconductor memory apparatus, e.g., first to fourth mats MAT0 to MAT3 in FIG. 1. Afterwards, the first to fourth mats MAT0 to MAT3 are enabled for a predetermined time, and the data stored in each of the first to fourth mats MAT0 to MAT3 is outputted after the predetermined time elapses. When a logic low data is outputted from the each of the first to fourth mats MAT0 to MAT3, this indicates that a micro-bridge (i.e., the leakage current flowing from the word line to the bit line) does not exist, whereas, if a logic high data is outputted from any one of the first to fourth mats MAT0 to MAT3, this indicates that a micro-bridge exists.
Since such a USD test is used to improve the reliability of the semiconductor memory apparatus, the test should be performed on all of the mats of the semiconductor memory apparatus under substantially the same condition. In the typical open bit line structure shown in FIG. 1, during the USD test, upper bit lines of a foremost mat (i.e., the first mat MAT0) are precharged to a bit line precharge voltage (VBLP) level and subsequently their voltage levels are not varied with time, whereas, when all of the mats are enabled, second to fourth mats MAT1 to MAT3 can have a high level bit line and a low level bit line by sense amplification operations of corresponding sense amplifier groups SA0 to SA3, respectively coupled thereto. Therefore, when the USD test is performed on the semiconductor memory apparatus having the open bit line structure, the USD test cannot be performed on all of the mats under substantially the same condition, thereby decreasing the reliability of the USD test.